ASIC Design Engineer
BBBH13232_1731356469
Posted: 11/11/2024
- US$200000 - US$250000 per annum + Equity Package
- Mountain View, California
- Permanent
Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control. Their scalable hardware enables faster model development and accessibility for researchers and startups.
Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems.
They are actively looking for a Principal ASIC Design Engineer.
Responsibilities:
- Contribute to silicon architecture-to-design methodology for scalability.
- Lead design from micro-architecture to sign-off ready stages.
- Drive reviews and collaborate with verification and physical design teams.
Requirements:
- Proven experience in silicon design from concept to production.
- Proficiency in SystemVerilog, Python, C/C++, and similar languages.
- Strong skills in high-performance compute and related functionalities.
- Experience in testing designs and achieving coverage goals.
- Hands-on experience with synthesis, equivalence checking, and design linting.
- Familiarity with DFT and physical design methodologies.
- Knowledge of verification and emulation platforms is a plus.
- Experience in silicon debug and bring-up is a plus.
If interested in joining them please apply here or reach out to Jwhitcomb@acceler8talent.com
Jake Whitcomb
Recruitment Executive