Acceler8 Talent is seeking a Principal ASIC/RTL Design Engineer to join a start-up that is pioneering in-memory compute to accelerate edge AI applications at extremely low power and compute efficiency.
Although still in stealth-mode, they have recently raised a large series-A round to give them runway for a couple of years. They have already taped-out a few chips with the most recent performing at 20 TOPS per Watt, which they expect to 5X with each future generation of chip.
- MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design.
- Industry Experience with Verilog and system Verilog
- Experience with pre-layout simulation and post-layout simulation
- Familiarity with RISC/Arm or other core architectures
- ASIC design of image processing systems
- Industry knowledge of SoC architecture such as CPU, GPU or accelerators