Chip & System Modeling Architect

Acceler8 Talent is seeking a Chip & System Modeling Architect to join an extremely well-funded semiconductor startup that has designed and developed a new class of switching fabric to eliminate IO bottlenecks in large distributed AI compute systems.

As a Chip & System Modeling Architect, you will report into the CTO and will collaborate with cross-functional teams to deliver high-performance simulation tools that model the functionality and performance of their complex switching fabric.

Responsibilities

• Develop and maintain the simulation methodology for performance modeling for the device architecture including queueing & packet processing models. Incorporate functional models into performance models.
• Own coding of the models in C/C++ and roadmap/strategy/interlocks for model development. Produce detailed documentation for the models, including pseudo-code and equivalence checking to RTL.
• Fully specify the methodology and software required to exercise the models; log results, perform regression testing, or correlate against functional and RTL DV simulations.
• Drive product architecture definition, tradeoffs, and validation in new areas/directions, including network / system / I/O virtualization, security, root of trust, system/board management.
• Leverage simulation efforts for customer validation by adjusting the model to per-customer variants, drive evolution of the models to achieve both customer and internal development goals.
• Create specifications for software and for microarchitecture teams, and collaborate closely with both teams towards meeting aggressive product specifications and schedules. o
• Drive innovations at the system and chip level to address technical challenges in front of the company.

Qualifications

• Significant experience in processor or networking chip architecture definition, modeling and/or validation at an industry or product category leader. o
• Must have coded and validated silicon/system behavioral models in C, systemC, or C++; experience with ns3 or other multi-node network simulators a plus.
• Hands-on knowledge and/or programming experience with distributed clusterscale applications.
• Track record of successful involvement in infrastructure product execution/deployment.
• Solid programming skills in C/C++; fluency in scripting languages (Python, Perl) desired. o
• Understanding of silicon chip architecture and fundamentals required; proficiency in Verilog/SystemVerilog and testbench creation a plus.

They are looking for someone to started right away and are offering $250k-$300k base. They have a strong preference for people in the San Francisco Bay Area, however they will consider 100% remote for the right candidate.

Please apply here or contact Luke at ltomaszko@acceler8talent.com to hear more.