We are seeking an experienced Verification Engineer to join an exciting and well-funded hardware acceleration start-up whose vision is to enhance neural network inference to unprecedented levels of performance, efficiency and scalability.
Responsibilities:
- Building, designing, planning and debugging robust verification environments.
- Execute verification strategy which ensure prototypes meet device and system level requirements.
- Convert product vision and design specifications into effective block-level and overall testing strategies.
Requirements:
- 10+ years experience in design verification of high performance chips.
- Knowledge of memory interfaces (DDR, LPDDR, etc.)
- Extensive experience in high performance IP verification, using low power techniques.
- Strong understanding of PCIe and other bus protocols.
- Expertise in SystemVerilog and experience with Python, Perl, or other scripting languages.
- Excellent Knowledge in UVM and Verilog coding.
Key Skills: Design Verification, UVM, PCIe, Ethernet, Bus Standards, Memory Bus, System Bus, Expansion Bus, Memory Interfaces (DDR, LPDDR, etc.), Python, Perl, etc.
