Acceler8 Talent is seeking an experienced Design Verification Engineer to join a well-funded ($50m series A) HW acceleration start-up that is developing a novel interconnect architecture which will eliminate congestion in massively distributed systems.
· Transform product vision and behavioral specifications into efficient block-level and top-level tests
· Incorporate state of the art verification techniques to tackle scaling and performance requirements
· Define and implement infrastructure for HW/SW co-simulation.
· Execute verification strategy which ensure prototypes meet device and system level requirements
· 8+ years industry experience in design verification
· Expertise verifying chip and block-level designs for high-performance networking chips
· Strong experience with full chip verification and infrastructure development.
· Expertise in SystemVerilog and experience with Python, Perl or another scripting language.
· Proven experience of quality, timely delivery of work on "shipped products"
· Excellent knowledge of UVM
Key Skills: Design Verification, UVM, OVM, Testbench, Testplan, SystemVerilog, Full chip verification