DFT Engineer

  • US$220000 - US$260000 per annum + Equity Package
  • Mountain View, California
  • Permanent

Acceler8 Talent is seeking a DFT Engineer to join a hardware start-up that is developing a new interconnect architecture to eliminate congestion in massively distributed systems and have recently raised a substantial Series A.

The founding team hail from leading hardware & tech companies and their major investor has a fantastic track record of turning early stage start-ups into successful companies.

Responsibilities o

  • As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
  • You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor
  • You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high speed I/O for the logic scan test
  • You will work with Physical Designers to validate the DFT timing constraints
  • You will work with RTL Designers to verify test design rules
  • You will work with Test Engineers to bring up the patterns on the ATE Automated Test Equipment o You will help develop and deploy DFT methodologies for our next generation products.


  • Master's degree in Electrical Engineering or equivalent practical experience.More than 7 years of hands-on experience in Design for Test (DFT) or closely related domains.
  • Profound expertise in crafting scan test plans, implementing Built-In Self-Test (BIST) methodologies for memories and IOs, fault modeling, Automatic Test Pattern Generation (ATPG), and fault simulation
  • Strong analytical prowess demonstrated in verifying and validating test patterns and logic across intricate, large-scale designs using industry-standard tools.
  • Comprehensive understanding of various facets including RTL and clock design, Static Timing Analysis (STA), place-and-route, and power optimization, facilitating informed trade-off decisions
  • Proven track record in silicon debug and ATE bring-up, encompassing familiarity with pattern formats, failure analysis, and test program development.
  • Proficient in programming and scripting languages such as Perl, Python, or Tcl, with a keen interest in staying updated with the latest advancements.
  • Exceptional communication skills, both written and verbal, coupled with a proactive mindset towards tackling complex challenges.

They are looking for someone to start ASAP and are offering $210k-$260k base with a generous equity package. Please apply here or contact me at Jwhitcomb@acceler8talent.com if you would like to hear more.

This position is open to Boston, Mountain View, Raleigh, and Austin.

Jake Whitcomb Recruitment Executive

Apply for this role