This early stage, Stanford spinout is at the forefront of state-of-the-art advancements in processing-in-memory technologies. Their architecture provides an entirely new way to accelerate encryption algorithms and now want to bring it to market.
Right now, they are in a phase of expansion - looking for an ambitious Digital Design Engineer who wants to expand the scope of their skillsets by contributing across all aspects of front-end design (uArchitecture, Chip Architecture, RTL Design, and Verification).
- MS or PhD in EE or related fields.
- Understanding of testbench design best practices.
- Industry or academia experience working with RISC pipelines/architectures.
Preferred Skills & Experience:
- Analog Design + Layout in Cadence Virtuoso.
- Experience with mixed-signal designs.
- Experience with low power or ultra-low power designs, eFlash.
- Timing handoff using Synopsys Liberty Format.
You also MUST be a US Citizen or Lawful Permanent Resident to qualify for this role.
Key Skills: RTL Design, Micro-architecture, Logic Design, ASIC Design, Analog Design, Mixed-Signal Design, Verilog/SystemVerilog, VHDL, C/C++, eFlash NVM IP, low power, ultra-low power, RISC architectures & pipelines, Cadence Virtuoso, Synopsys Liberty.
Please apply here or contact me at email@example.com to hear more.