Digital Design Engineer

Location Scotia
Discipline: Hardware Acceleration Jobs
Job type: Permanent
Salary: US$100000 - US$160000 per annum
Contact name: Nicolas Roselli

Contact email:
Job ref: BBBH15045_1683637157
Published: 24 days ago

This early stage, Stanford spinout is at the forefront of state-of-the-art advancements in processing-in-memory technologies. Their architecture provides an entirely new way to accelerate encryption algorithms and now want to bring it to market.

Right now, they are in a phase of expansion - looking for an ambitious Digital Design Engineer who wants to expand the scope of their skillsets by contributing across all aspects of front-end design (uArchitecture, Chip Architecture, RTL Design, and Verification).


  • MS or PhD in EE or related fields.
  • Verilog/SystemVerilog/VHDL
  • C/C++
  • Understanding of testbench design best practices.
  • Industry or academia experience working with RISC pipelines/architectures.

Preferred Skills & Experience:

  • Analog Design + Layout in Cadence Virtuoso.
  • Experience with mixed-signal designs.
  • Experience with low power or ultra-low power designs, eFlash.
  • Timing handoff using Synopsys Liberty Format.

You also MUST be a US Citizen or Lawful Permanent Resident to qualify for this role.

Key Skills: RTL Design, Micro-architecture, Logic Design, ASIC Design, Analog Design, Mixed-Signal Design, Verilog/SystemVerilog, VHDL, C/C++, eFlash NVM IP, low power, ultra-low power, RISC architectures & pipelines, Cadence Virtuoso, Synopsys Liberty.

Please apply here or contact me at to hear more.