Acceler8 Talent is actively seeking a DFT Lead Engineer to join a leading AI semiconductor start-up company that has recently closed a large Series C round of funding and created never before seen embedded controllers and fusion processors that eliminate developers having to use multiple platforms for AI & ML edge processing.
This is the one of the first semiconductor companies in the US to have a partnership with ARM and have access to their latest cores.
Their founder and CEO already has already taken one company public, growing the companies revenue to over 7 billion dollars and is planning to do the same with this company.
- Define & document DFT requirements/Specifications for IP/Block and Chip level
- Execute DFT Lint to identify scan DRC violations and resolution
- Plan and Insert MBIST and memory repair
- Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests
- Expert knowledge of Mentor Tessent toolchain
- 7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success
- Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
- Hands-on hierarchical DFT flow experience from RTL to netlist
- Experience in inserting EDT, wrapper cells and OCC
- Experience in analyzing DFT DRC violations and fault coverage analysis