Lead DFT Engineer

  • US$220000 - US$260000 per annum + Equity package
  • Pleasanton, California
  • Permanent

Acceler8 Talent is partneredd with the fastest growing AIoT Acceleration company in the US. They are actively looking for a Manager of DFT.

Since being founded in 2019 by an industry veteran, They have closed their series C, completed one successful tapeout and are one of the first semiconductor companies in the US to have a partnership with ARM and have access to their latest cores.

This company has trademarked a single chip solution to the design of any accelerated AI/ML complex systems.


  • Define & document DFT requirements/Specifications for IP/Block and Chip level
  • Execute DFT Lint to identify scan DRC violations and resolution
  • Plan and Insert MBIST and memory repair
  • Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests
  • Expert knowledge of Mentor Tessent toolchain


  • 10+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success
  • Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
  • Hands-on hierarchical DFT flow experience from RTL to netlist
  • Experience in inserting EDT, wrapper cells, and OCC
  • Experience in analyzing DFT DRC violations and fault coverage analysis
Jake Whitcomb Recruitment Executive

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