Physical Design Engineer

Acceler8 Talent is seeking a MTS Physical Design Engineer to join a hardware start-up that is developing a new interconnect architecture to eliminate congestion in massively distributed systems and have recently raised a substantial round of funding for $125 million.

The founding team hail from leading hardware & tech companies and their major investor has a fantastic track record of turning early stage start-ups into successful companies.

Responsibilities

• Construct and support the CAD tool flow for physical implementation in a cloud-first development environment.
• Work closely with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders
• Define and build the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies.
• Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout.

Requirements

• Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience
• Expertise with STA
• Strong industry experience with Logic Equivilance Check
• Deep industry experience with the latest CAD tools through the entire physical design workflow
• Experience with circuit analysis using HSPICE is a plus
• Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages

They are looking for someone to start ASAP and are offering $200k-$250k base with a generous equity package. Please apply here or contact me at Jwhitcomb@acceler8talent.com if you would like to hear more.

This position is open to Boston, Mountain View, Raleigh, and Austin.