We are seeking an experienced Physical Design Engineer to join an exciting, well-funded start-up whose vision is to erase bottlenecks in decentralizes systems through novel interconnect innovations - a market that is expected to grow 12.6% each year ($21 billion by 2030).
- Develop and maintain CAD Design tool flow for physical implementation in a cloud-based development environment.
- Outline and build key physical components, including clock/reset design, power distribution system, and interconnect topologies.
- Collaborate with architecture team for chip-level floorplan and block partitioning.
- Carry out physical implementation at block, cluster and top levels - from synthesis, layout and power optimization to PnR, timing closure, physical verification and final tape-out.
- Mentor junior engineers.
- MSEE/CE and 4+ years' experience.
- Expertise in SystemVerilog and Perl, Python or other scripting languages.
- Industry experience in the physical implementation of large, high-performance chips (CPUs, GPUs, Smart-NICS, Network Interface controllers, or latest silicon process nodes)
- Experience working on Network Switching/Routing Fabrics (Ethernet, Infiniband, HPC) preferred but not required.
Key Skills: Physical Design, Physical Implementation, System Verilog, Scripting Languages (Perl, Python, etc.), Ethernet, Infiniband, CPUs, GPUs, Smart-NICS, Large High Performance Networking Fabrics.