Acceler8 Talent is seeking a Physical Design Lead to join a very well funded I/O acceleration start-up which has just raised a $50m series A to develop a new advanced interconnect architecture to reduce congestion in massively distributed systems, helping networks & data centers keep up with the increasing demands of modern computing.
- Evaluate tool flow for physical implementation in a cloud-first environment.
- Work on chip-level floorplan and block partitioning. Evaluate tradeoffs in interface complexity, block size and functional partitioning.
- Define and construct major physical structures, including clock architecture, power delivery network, and interconnect topologies.
- Establish the P+R workflow at block & chip levels, working with large and complex designs in the latest process technology nodes.
- Lead block and top-level physical implementation, from floorplan & power plan, through P+R & timing closure.
- 10+ years experience in the physical implementation of high-performance network switching/routing silicon, such as: SmartNICs, PCIe, DPUs, high-speed serial interfaces etc.
- Proven technical leadership and execution on shipped products
- Experience working on the latest advanced nodes
- Expertise in SystemVerilog and experience with Python, Perl or other scripting language.
- Deep experience with the latest CAD tools.
- Familiarity with a variety of analysis tools
They are looking for someone to started right away and are offering $200k-$220k base with a very generous equity package. Please apply here or contact Luke at email@example.com to hear more.