Principal Design Verification Engineer

  • US$200000 - US$275000 per annum + Equity Package
  • Mountain View, California
  • Permanent

Acceler8 Talent has recently partnered with a company that is redefining AI hardware, focusing on maximizing performance for large language models (LLMs) like GPT. With a commitment to cost efficiency and optimizing performance-per-dollar, their technology offers competitive latency and low-level hardware control. Their scalable hardware enables faster model development and accessibility for researchers and startups.

Founded by two previous leaders of a FAANG company, they are leading the charge as the compute platform for AGI, crafting comprehensive solutions from silicon to systems.

They are actively looking for strong Design Verification Engineers.


  • Develop scalable verification methods for MatX across blocks, subsystems, and full-chip.
  • Manage verification execution for subsystems and chips, creating testbenches and tests to achieve coverage closure.
  • Lead verification reviews for test plans, progress, and closure to meet silicon milestones, including design freeze and tapeout.


  • Extensive experience leading verification from concept to silicon production.
  • Proficiency in SystemVerilog, Python, C/C++, Bluespec, and similar languages for verification and silicon modeling.
  • Expertise in advanced verification methodologies like UVM, assertion-based verification, and formal verification.
  • Demonstrated ability to develop portable tests and drivers for silicon validation and post-silicon debug.
  • Deep understanding of silicon micro-architecture and design principles, particularly in high-performance compute, high-speed connectivity, and memory management.
  • Knowledge of emulation and prototyping platforms and methodologies is advantageous.
  • Hands-on experience in silicon debug and bring-up is a plus.

If interested in joining them please apply here or reach out to

Jake Whitcomb Recruitment Executive

Apply for this role