Principal Design Verification Engineer

BBBH9275_1717679489
  • US$220000 - US$250000 per annum + + Bonus + Equity
  • Mountain View, California
  • Permanent

Acceler8 Talent is seeking a Principal Design Verification Engineer to join a networking startup that has developed a novel fabric architecture which promises to cut the cost of LLMs and GenAI by up to 50%.

This company has just raised a large series-B round ($125m) to give them runway for a couple of years and are on track bring their first chip to market at the end of 2023.

  • Transform product vision and behavioral specifications into efficient block-level and top-level tests
  • Incorporate state of the art verification techniques to tackle scaling and performance requirements
  • Define and implement infrastructure for HW/SW co-simulation.
  • Perform verification strategy to ensure prototypes meet device and system level requirements

Requirements

  • 10+ years industry experience in design verification
  • Expertise verifying chip and block-level designs for high-performance networking chips
  • Strong experience with full chip verification and infrastructure development.
  • Expertise in SystemVerilog and experience with Python, Perl or another scripting language.
  • Proven experience of quality, timely delivery of work on "shipped products"
  • Excellent knowledge of UVM

The ideal candidate will have the versatility to build infrastructure and tests for both ASIC and FPGA platforms. C++ or SystemC knowledge is also highly desirable.

They are looking for someone to start ASAP and are offering $220k-$250k base + sign-on bonus and a generous equity package. Please apply here or contact Luke at ltomaszko@acceler8talent.com to hear more.

Luke Tomaszko Managing Recruitment Executive & Hardware Team Lead

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