Acceler8 Talent is seeking an experienced Principal Physical Design Engineer to join a well funded hardware acceleration start-up that is developing the next generation of interconnect technology to eliminate bottlenecks in distributed systems, a market worth almost $6 billion annually with a CAGR of 14.5%
- Evaluate tool flow for physical implementation in a cloud-first environment.
- Work on chip-level floorplan and block partitioning. Evaluate tradeoffs in interface complexity, block size and functional partitioning.
- Define and construct major physical structures, including clock architecture, power delivery network, and interconnect topologies.
- Establish the P+R workflow at block & chip levels, working with large and complex designs in the latest process technology nodes.
- Lead block and top-level physical implementation, from floorplan & power plan, through P+R & timing closure.
- 8+ years experience in the physical implementation of large complex SoCs, such as SmartNIC, modems, switches or routers.
- Proven execution on shipped products
- Experience working on the latest advanced nodes
- Expertise in SystemVerilog and experience with Python, Perl or other scripting language.
- Deep experience with the latest CAD tools.
- Familiarity with a variety of analysis tools
They are looking for someone to started right away and are offering $200k-$250k base with a very generous equity package. Please apply here or contact Luke at firstname.lastname@example.org to hear more.