Acceler8 Talent is seeking an experienced RTL Design Engineer to join an exciting and well funded I/O acceleration start-up. This start-up is designing a new interconnect architecture to reduce congestion in massively distributed systems, helping keep up with the increasing demands of modern computing.
- Own block design, from analysis of the design approach through to RTL implementation.
- Deliver high performance, robust design to meet timing, testability and power requirements
- Outline functional and performance requirements in the development of high throughput engines
- Support verification, from development of test plans through to execution of the testing phases.
- Support silicon bring up and post-silicon testing
- 5+ years industry experience in logic design, from design specification to RTL design to implementation.
- Familiarity with P+R constraints, synthesis and static timing analysis
- Expertise in SystemVerilog and experience with Python, Perl or other scripting language.
- Proven experience of quality, timely delivery of work on "shipped products"
They are looking for someone to start right away and are offering $150k-$200k base with a generous equity package. Please apply here or contact Luke at firstname.lastname@example.org to hear more.