Acceler8 Talent is seeking a Principal level RTL Design Engineer to join a hardware start-up that is developing a new interconnect architecture to eliminate congestion in massively distributed systems and have recently raised a substantial Series A.
The founding team hail from leading hardware & tech companies and their major investor has a fantastic track record of turning early stage start-ups into successful companies.
- Own all aspects of the logic design process, from analysis of the design.
- Deliver a robust, high performance design that meets the timing, area, reliability, testability, and power requirements set by a cross-functional engineering team.
- Outline functional and performance requirements in the development of high throughput engines
- Support verification, from development of test plans through to execution of the testing phases.
- Support silicon bring up and post-silicon testing
- Minimum BSEE/CE + 7 years or MSEE/CE + 5 years experience
- Industry experience with High-performance Network Interface Controllers, Smart-NICs, or DPUs processing pipelines with multi-threaded datapaths and ordering capabilities.
- Professional experience with packet buffering subsystems. Demonstrating thorough knowledge of traffic management concepts encompassing queueing, scheduling, thresholding, admission control, flow control, and memory bandwidth.
- Expert knowledge of SystemVerilog
They are looking for someone to start ASAP and are offering $150k-$200k base with a generous equity package. Please apply here or contact Jake at Jwhitcomb@acceler8talent.com if you would like to hear more.
This position is open to Boston, Mountain View, Raleigh, and Austin.