Acceler8 Talent is seeking a Principal Design Verification Engineer to join an AI acceleration that is pioneering in-memory computing to accelerate AI at the edge.
This company has just raised a substantial series-A round to give them runway for a couple of years. They have already taped-out their first chip and have started work on their second generation data center ASIC, which they aim to bring to market in the next couple years.
- Transform product vision and behavioral specifications into efficient block-level and top-level tests
- Incorporate state of the art verification techniques to tackle scaling and performance requirements
- Define and implement infrastructure for HW/SW co-simulation.
- Perform verification strategy to ensure prototypes meet device and system level requirements
- 6+ years industry experience in design verification
- Expertise verifying chip and block-level designs for high-performance networking chips
- Strong experience with full chip verification and infrastructure development.
- Expertise in SystemVerilog and experience with Python, Perl or another scripting language.
- Proven experience of quality, timely delivery of work on "shipped products"
- Excellent knowledge of UVM
The ideal candidate will have the versatility to build infrastructure and tests for both ASIC and FPGA platforms. C++ or SystemC knowledge is also highly desirable.
They are looking for someone to start ASAP and are offering $200k-$250k base with bonus, sign-on and a very generous equity package. Please apply here or contact Luke at firstname.lastname@example.org to hear more.