Acceler8 Talent is seeking a Senior Physical Design Engineer to join one of the world's leading fabless semiconductor companies, known for their dominance of the personal and mobile communication market.
You will be joining their highly successful Austin based CPU team and will be responsible for high performance CPU implementation in advanced nodes as small as 3nm for their flagship mobile SoC, which has won plaudits around the world for packing incredible performance for the cost.
Requirements
- 4+ years of experience in physical design of high performance CPUs with frequencies greater than 2GHz
- Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
- Experienced in different clocking techniques including CTS, multi-source CTS, datapath and concurrent clock optimization.
- Experienced in working on advanced finfet process nodes and developing implementation flows
- Sign-off experience meeting signal integrity, power integrity, and DFM requirements.
- Strong skills with Cadence or Synopsys Implementation tools.
- Understanding of STA and timing constraints.
- Scripting skills in tcl, perl, or python.
Addition useful skills
- ARM CPU implementation experience
- Experience with structured datapath implementation.
- STA & timing closure
- IR Drop analysis (Static & Dynamic)
Key Skills: Physical Design, Physical Implementation, STA, timing closure, CPU implementation, hierarchical design, implementation flows, implementation
