Acceler8 Talent is seeking a Senior Principal Design Verification Engineer to join an well-funded AI acceleration start-up which is poised to deliver the industry's most disruptive in-memory compute technology for AI at the edge.
This DV Engineer will be responsible for leading the verification activities and architecting verification infrastructure for their analog/mixed signal in-memory AI processor.
- Transform product vision and behavioral specifications into efficient block-level and top-level tests
- Incorporate state of the art verification techniques to tackle scaling and performance requirements
- Define and implement infrastructure for HW/SW co-simulation.
- Execute verification strategy which ensure prototypes meet device and system level requirements
- 10+ years industry experience in design verification
- Expertise verifying chip and block-level designs for large, complex SoCs.
- Strong experience with full chip verification and infrastructure development.
- Ability to take ownership of blocks
- Expertise in SystemVerilog and experience with Python, Perl or another scripting language.
- Excellent knowledge of UVM
- Experience verifying RISC-V or ARM cores or AI acceleration chips.
They are looking for someone to start ASAP and are offering $200k-$250k base with bonus, sign-on and a very generous equity package. Please apply here or contact Luke at firstname.lastname@example.org to hear more.