SoC ASIC Design Engineer

BBBH13232_1715792358
  • US$200000 - US$230000 per annum + Equity Package
  • San Jose, California
  • Permanent

Acceler8 Talent has recently partnered with a leading startup specializing in next-generation interconnect technologies designed for the future of HPC and AI applications. The company has successfully closed a large Series A funding round and secured a significant partnership with a global industry leader.

They are looking for a Senior/Principal SoC/ASIC Design Engineer who is an expert with PCIe and CXL to help them accelerate AI cloud computing.

You would be working with architecture definition and modeling, micro-architecture specification, and industry standard compliance. This includes defining design partitioning for efficient implementation and providing feedback on verification plans. You will also drive development at various levels, collaborate across teams for robust IP delivery, and actively participate in post-silicon validation.

Requirements:

-10-15 years of Verilog/System Verilog logic design experience

- Proven track record in bringing chips from concept to production

- Expertise in complex ASIC design

- Understanding of ASIC design methodologies and flows

- Proficiency in standard techniques like architecture definition, design partitioning, and clock domain design

- Strong knowledge of Synthesis, STA, CDC, Lint, and Perl scripting

- Familiarity with PCIe/CXL and peripheral protocols such as UART, I2C, SPI Flash

If you are interested in working on the forefront of interconnect technologies and accelerating AI cloud computing please apply here or feel free to reach out directly at Jwhitcomb@acceler8talent.com

Jake Whitcomb Recruitment Executive

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