Sr/Principal Low Power Digital Implementation Engineer

Location San Francisco
Discipline: Hardware Acceleration Jobs
Job type: Permanent
Salary: US$180000 - US$240000 per annum + Equity package, Annual Bonus
Contact name: Jake Whitcomb

Contact email: jwhitcomb@acceler8talent.com
Job ref: BBBH11692_1674513419
Published: 13 days ago
Startdate: ASAP

Acceler8 Talent is partnered with the fastest growing AIoT Acceleration company in the US. They are actively looking for a Principal Digital Low power implementation engineer to join them.

They have created two devices that offers developers a single chip solution to complex systems that require accelerated AI/ML edge processing.

Since being founded in 2019 by an industry veteran, this company has closed their series C, successfully taped out a chip, and opened 4 offices (2 outside of the US).

They are looking for an Engineer to own the UPF delivery of various blocks and chip top level.

Responsibilities

  • Define UPF-based low power methodology and scripts/flows
  • Interface with Physical Design for design partitioning, floorplan and timing closure
  • Critique UPF implementation and enhance design changes and ECOs

Requirements

  • Expert level experience with UPF based low power ASIC Implementation.
  • Vast experience in low power design issues, tools, and methodology including UPF power intent specification
  • Strong understanding of Synthesis (Cadence), DFT (Tessent) and back-end (Cadence) tools
  • Strong Experience with Clock Domain Crossing (CDC) Analysis

They are offering a Hybrid remote work schedule out of their Pleasanton or Irvine, California offices.

If you have an interest in this position or know someone who does please apply here or you can reach out to me directly at Jwhitcomb@acceler8talent.com