Headquartered in San Jose, CA this well-funded startup ($56 million) has created a new type of security processor in servers and network infrastructure. Their award-winning AI-enhanced solution is the first of its kind, redefining the management and control of all digital systems.
As a Design Verification Engineer, you will join a brilliant team responsible for RTL SoC/Subsystem Verification of ARM-based CPU's and work on methodologies like UVM, Portable Stimulus and other formal verification flows.
What can be offered to a Senior Staff Verification Engineer:
- An opportunity to help push the envelope on silicon-based approach to cybersecurity.
- Competitive base salary + equity packages.
- A beautiful office located in San Jose, CA
Key Skills: UVM Verification & Environment Development, Test Plan Definition, C, Assembly, SystemVerilog, RTL/Gate-level Simulation, Functional Test Vector Development, Scripting Languages (Perl, Python, Shell), Power-Aware Verification (a plus).