Application Specific Integrated Circuit Design Engineer

Microarchitect & RTL Design Engineer

Hybrid | Mountain View, CA

Acceler8 Talent is seeking an experienced Microarchitect & RTL Design Engineer to join a well funded startup whose hardware promises to drastically change the economics of compute for the worlds' largest models.

With >$100m series A in the bank, and a genuinely world-class team with a track record of shipping highly successful products, this company abandons legacy chip design assumptions and strives for the best possible solution for every aspect of their chip - there is no such thing as "good enough".

As a Microarchitect & RTL Design Engineer, you will be responsible for defining microarchitecture and implementing performance-critical RTL. You will work closely with architecture, verification, compiler, and software teams to translate architectural intent into high-quality, production-ready silicon.

Responsibilities:

• Design, implement, and debug RTL blocks at the subsystem and full-chip level for custom AI accelerators
• Translate architectural specifications into synthesizable, high-performance RTL
• Collaborate closely with architecture, verification, physical design, and software teams to ensure correct, performant, and scalable implementations
• Optimize RTL for performance, power, and area (PPA) across compute, memory, and interconnect subsystems
• Support integration, timing closure, bring-up, and debug through tape-out and silicon validation

Requirements:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent experience
• Strong experience designing RTL in SystemVerilog or Verilog for complex digital systems
• 5+ years in microarchitecture/RTL design focused position in industry.
• Experience implementing performance-critical logic, including pipelines, state machines, memory interfaces, and on-chip interconnects
• Solid understanding of computer architecture and micro-architecture, particularly for high-performance compute or accelerator designs

Preferences:

• Experience working on AI accelerators, GPUs, or high-performance SoCs
• Familiarity with hardware–software interfaces, including how RTL design choices impact kernels, compilers, and system software
• Experience supporting post-silicon bring-up and debug

If you're interested in building the future of AI compute, apply here or reach out to me at ltomaszko@acceler8talent.com to discuss further.