Logic Design Engineer

Acceler8 Talent is seeking an experienced RTL Engineer to join an early-stage startup building a compute platform for AGI. This is a chance to own the full-chip RTL assembly process, collaborate across subsystems, and ensure the world’s most advanced AI silicon comes together into a seamless, production-ready product.

They're looking for a Top-Level Integration expert to drive the assembly, integration, and validation of their chips. In this role, you will own the top-level RTL integration flow, ensuring that subsystems come together into a performant, functionally correct, and sign-off full-chip design.

Responsibilities:

• Own the top-level RTL integration of large, complex SoCs from subsystem drop to sign-off.
• Develop and maintain integration methodologies for scalable assembly across full-chip builds.
• Drive chip-level reviews of connectivity, functionality, timing, and PPA closure across milestones (integration freeze, design freeze, tapeout).
• Work closely with subsystem owners, verification, DFT, and physical design teams to resolve integration issues and ensure clean handoff to downstream flows.
• Debug and resolve top-level RTL issues (connectivity mismatches, CDC/RDC, resets, clocks, design lint) across the chip hierarchy.
• Deliver sign-off quality RTL suitable for synthesis, equivalence checking, and emulation.

Requirements:

• Hands-on experience with top-level RTL integration of ASICs or SoCs, from subsystem assembly through production silicon.
• Strong skills in SystemVerilog for integration and debugging; familiarity with Python, C/C++, or scripting languages to support integration flows.
• Deep knowledge of chip-level design concepts: clocks, resets, power domains, CDC/RDC, lint, connectivity, and hierarchical build flows.
• Experience with synthesis and sign-off flows (equivalence checking, lint, DFT/scan stitching, power/timing checks).
• Proven track record of working across multi-disciplinary teams (design, verification, physical design, DFT) to achieve high-quality tapeouts.
• Plus: familiarity with emulation platforms and methodologies.
• Plus: experience with silicon bring-up and debug.