RTL Design Engineer (Top Level Integration)
GW74
Posted: 30/09/2025
- $250,000-$300,000
- Mountain View, CA
- Permanent
About the job
ASIC Top-Level Integration Engineer – Datacenter AI Hardware
Acceler8 Talent is partnering with a well-funded startup (>$100m Series A), backed by world-class investors, to hire an experienced Top-Level Integration Engineer.
This team is building the next-generation compute platform for companies developing and running GenAI models. Led by ex-Google engineers who were instrumental in the development of Google's AI capabilities, it's safe to say the team has skin in the game.
You’ll join a highly skilled engineering group at the forefront of silicon design, driving the integration of complex subsystems into full-chip solutions from architecture through to production silicon.
What You’ll Do
- Own top-level chip integration, bringing together compute, interconnect, and memory subsystems into production-quality ASIC/SoC designs.
- Develop and maintain integration flows for RTL assembly, clock/reset/power architecture, and chip-level interfaces.
- Collaborate across design, verification, DFT, and physical design teams to achieve full-chip functionality, timing, and coverage closure.
- Drive chip-level build, simulation, and debug flows, ensuring quality sign-off for synthesis, lint, CDC, and equivalence checking.
- Work closely with verification and emulation teams to validate full-chip integration and debug issues across subsystems.
- Support silicon bring-up, debug, and performance validation at the top level in the lab.
What We’re Looking For
- Proven track record of chip-level integration from architecture spec through production silicon.
- Strong experience with SystemVerilog and proficiency in Python, C/C++, Bluespec, or similar languages for design and automation.
- Hands-on expertise in RTL integration flows including lint, CDC, synthesis, and equivalence checking.
- Solid understanding of DFT and physical design concepts, with experience partnering across disciplines to achieve sign-off.
- Familiarity with full-chip verification and emulation; hands-on bring-up experience is a strong plus.
Why Join?
- Join a well-funded, fast-growing startup shaping the future of GenAI compute.
- Work alongside industry-leading architects and engineers.
- Hybrid role based in Mountain View, CA (3 days on-site).
- Immediate start available.
If you’re interested, apply here or reach out directly to Luke at ltomaszko@acceler8talent.com to learn more.
Luke Tomaszko
Senior Semiconductor & Chip Design Recruiter