RTL Design Manager

Acceler8 Talent is partnering with a well-funded AI chip startup ($500M Series B) to hire an experienced SoC Micro-Architecture & RTL Design Lead (Manager).

Led by industry leaders who were instrumental in the development of Google’s TPU, and who bring deep expertise in high-performance computing and large-scale silicon development, the company is building a full-stack compute platform designed to train and run the largest machine learning models efficiently and sustainably.

You’ll lead a team of micro-architects and RTL designers responsible for delivering high-performance silicon across compute, memory management, and high-speed connectivity subsystems. This role sits at the heart of the silicon organization, driving architecture execution from concept through production and enabling the performance and scalability required for next-generation AI infrastructure.

What You’ll Do

• Lead and manage a team of micro-architects and RTL designers responsible for subsystem and chip-level design
• Hire, mentor, and grow a world-class silicon design team capable of delivering high-performance compute architectures
•  Drive silicon development from architecture specification through production silicon in collaboration with cross-functional teams
•  Oversee the delivery of high-quality micro-architecture specifications and RTL designs to downstream teams including verification, physical design, and DFT
•  Coordinate handoff processes between the RTL design team and partner teams across silicon, software, and system engineering
•  Partner with other technical leaders to co-develop silicon architecture and execution strategies across compute, connectivity, and memory subsystems
• Guide IP selection and vendor/tool decisions for silicon development and related infrastructure
• Work with executive leadership on hiring plans, budgeting, and resource planning to support silicon development
• Lead technical reviews within the team and across engineering organizations to ensure architectural integrity and execution quality

What We’re Looking For

• 10–20 years of experience in silicon development with deep expertise in SoC or ASIC architecture and RTL design
• At least 5 years of experience leading teams of micro-architects and RTL designers delivering complex silicon systems
• Proven concept-to-silicon experience developing subsystems or top-level SoC functions for high-performance compute platforms
• Strong leadership experience building and managing high-performing silicon design teams
• Hands-on expertise with SystemVerilog and modern hardware design methodologies
• Proficiency with programming and scripting languages used in chip development flows such as Python, C/C++, or similar
• Track record of delivering production silicon used in CPUs, GPUs, accelerators, or other high-performance compute platforms
• Strong experience working in fast-paced, cross-functional environments with shared ownership across silicon, software, and systems teams
• Ability to remain technically hands-on when required and lead deep architectural or RTL design discussions with engineering teams