Senior Design Verification Engineer

Acceler8 Talent is looking for a driven and energetic Design Verification Engineer to join an early-stage start-up developing foundational technology to support the next generation of AI systems. Founded by experienced engineers across semiconductors, AI platforms, and software, the team is focused on enabling intelligent devices, more efficient data centers, and entirely new categories of AI-driven applications.

The team is scaling rapidly and is seeking engineers who enjoy solving hard problems and pushing technical boundaries in AI hardware and software. This role offers the opportunity to work with a highly experienced group and contribute directly to technology with global reach and long-term impact.

As a Senior ASIC Design Verification Engineer, you will take ownership of verifying key components of an AI inference chiplet designed to support models ranging from very small to extremely large.

Responsibilities include:

• Owning verification planning and execution at both fabric-level and full-chip scope, ensuring thorough validation across multiple design layers
• Working closely with architecture, firmware, and design teams to translate specifications into detailed and effective verification plans
• Developing sophisticated verification environments, including constrained-random stimulus, checkers, scoreboards, and assertions to validate functionality and coverage
• Defining and executing end-to-end verification strategies, including coverage analysis, regression automation, and data-driven optimization of verification quality
• Promoting strong verification practices through code reviews, sprint-based execution, and structured feature rollout
• Exploring and adopting new verification methodologies, automated workflows, and emerging tools, including AI-assisted verification techniques

What You Bring

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field
• Experience: 5-10+ years of hands-on verification experience, including test planning, environment development, test creation, and debugging across IP, SoC, and system-level designs
• Domain Expertise: Deep experience with fabric-level and full-chip verification approaches and best practices
• Technical Skills: Strong proficiency in SystemVerilog/Verilog, UVM, and C/C++, including embedded software development and validation for RISC-based processors
• Verification Leadership: Proven ability to build scalable verification infrastructures, apply coverage-driven verification, and implement assertion-based verification methodologies