Senior Design Verification Engineer

Senior Design Verification Engineer - AI Hardware 

Hybrid from Mountain View, CA

Acceler8 Talent is seeking an experienced Design Verification Engineer to join a well funded startup whose hardware promises to drastically change the economics of compute for the worlds' largest models.

With >$100m series A in the bank, and a genuinely world-class team with a track record of shipping highly successful products, this company abandons legacy chip design assumptions and strives for the best possible solution for every aspect of their chip - there is no such thing as "good enough".

As a Senior Design Verification Engineer, you’ll own verification planning and execution at the full chip and subsystem level, defining test plans, creating testbenches, and owning verification toward various silicon milestones. This is a hybrid role based in Mountain View, CA.

This role might be ideal for you if you have:

• Experience driving verification from concept-to-silicon
• 8+ years working in design verification
• Excellent SystemVerilog knowledge
• Experience with Python, C/C++, Bluespec or similar scripting and programming languages for verification and silicon modeling
• Production experience with advanced verification methodologies (UVM, ABV, formal verification, etc.)
• Strong understanding of silicon micro-architecture and design concepts used in high-performance compute, high-speed connectivity, memory management, and related functionalities
• Experience verifying data center/networking chips at subsystem or full chip level.

Familiarity with emulation and prototyping platforms and methodologies and hands-on experience with participation in silicon debugging and bring-up are pluses!

If you're interested in building the future of AI compute, apply here or reach out to me at ltomaszko@acceler8talent.com to discuss further.