Design Verification Engineer

Acceler8 Talent

Design Verification Engineer

Inference ASICs | Stealth Start-Up

The opportunity

Acceler8 Talent is partnering with a stealth AI chip startup developing silicon for inference. The team is looking for a hands-on Design Verification Engineer who wants meaningful ownership of complex digital blocks and subsystems, with direct influence on design quality.

You will work closely with designers to uncover difficult corner cases, investigate failures and establish confidence in the hardware. This is an opportunity for an autonomous engineer who enjoys building, debugging and making detailed technical decisions within an early team.

Technical scope

The work focuses on proving the behavior of digital hardware under realistic operating conditions and difficult corner cases. You will connect the design specification to a practical verification approach, deciding which scenarios need directed tests, which benefit from broader stimulus and how failures should be checked. A key part of the role is understanding whether an observed mismatch comes from the design, the test environment or an incorrect interpretation of the intended behavior.

What you will do

• Own verification of substantial digital ASIC blocks or subsystems, from understanding the design intent to validating fixes.
• Develop verification plans, environments and tests that exercise normal operation and challenging corner cases.
• Reproduce failures and trace bugs through the test environment and RTL to isolate the underlying cause.
• Partner with design engineers on corrective changes and demonstrate that issues are resolved.
• Improve verification effectiveness through clear technical reasoning, reusable infrastructure and focused debugging.
• Review block and subsystem specifications with designers, clarify ambiguous behavior and identify verification risks before they become late-stage debug problems.
• Build checks and stimulus that expose interactions between control logic, state transitions and data flow, including boundary conditions and competing events.
• Reduce complex failures to reproducible cases, document the mechanism and use targeted tests to confirm that fixes address the original issue without introducing regressions.

What you will bring

• Hands-on ownership of digital ASIC or SoC verification, with clear examples of your own implementation and technical decisions.
• Ability to explain a difficult bug from initial exposure through reproduction, root cause and validated resolution.
• Strong understanding of digital logic and the interaction between microarchitecture and verification.
• Comfort working independently, collaborating directly with designers and taking ownership in a small team.
• Experience translating design intent into a verification strategy, including stimulus design, expected behavior and meaningful pass or fail criteria.
• Ability to read RTL, interpret waveforms and logs, and distinguish a testbench problem from an underlying design defect.
• Clear communication of verification risks, open issues and the evidence needed to establish confidence in a block or subsystem.

Useful experience

• Verification of compute engines, CPUs, GPUs, inference accelerators or other complex digital ASICs.
• SystemVerilog, UVM, assertions and reusable verification infrastructure, or comparable experience with other verification methods.
• Around 5–10 years of relevant experience is a useful guide; strong engineers outside this range are also relevant.