RTL Design Engineer

RTL Design Engineer

Inference ASICs | Stealth Startup

The opportunity

Acceler8 Talent is partnering with a stealth AI chip startup developing silicon for inference. The team is looking for a hands-on RTL Design Engineer to translate microarchitecture into robust digital logic and take direct responsibility for implementation and debug.

You will join an early engineering team where individual contribution matters. The opportunity suits an engineer who enjoys working through detailed design problems, evaluating alternatives and staying close to the logic rather than moving away from implementation.

Technical scope

The role combines detailed digital design with the reasoning behind an implementable microarchitecture. You will work through how state, control and data move through your blocks, how boundary conditions are handled and how the implementation behaves when operations interact. You should be comfortable moving from a high-level requirement into synthesizable RTL, then using verification results and implementation feedback to refine the design.

What you will do

• Implement digital ASIC RTL from microarchitectural requirements and contribute to detailed design decisions.
• Work through logic behavior, corner cases and implementation constraints to produce correct, maintainable designs.
• Investigate challenging RTL and microarchitecture issues and make specific, validated design changes.
• Collaborate directly with verification engineers to reproduce failures and establish correctness.
• Work with implementation engineers to understand feedback and refine the design.
• Communicate design trade-offs clearly and take ownership of the blocks and technical decisions you deliver.
• Develop clear block-level design intent, including interfaces, sequencing and corner-case behavior, so verification and implementation engineers can work from a shared understanding.
• Evaluate alternatives for control and data-flow logic, explaining how each choice affects correctness, complexity and implementation constraints.
• Debug failures using RTL, waveforms and focused experiments, then work with verification engineers to demonstrate that design changes resolve the issue.
• Review feedback on timing, area or power where relevant to your block and consider RTL changes that address the underlying implementation constraint.

What you will bring

• Personally delivered digital ASIC or SoC RTL, with substantial hands-on design and debug ownership.
• Strong digital logic and microarchitecture fundamentals, with the ability to explain detailed design decisions.
• Evidence of resolving a difficult logic or microarchitecture problem through your own implementation changes.
• Ability to work independently and collaborate effectively across design, verification and implementation.
• Ability to turn requirements into a detailed implementation and reason about state machines, sequencing, interfaces and data-path behavior.
• Practical understanding of synthesizable RTL and how coding and microarchitectural decisions affect downstream implementation.
• A clear account of your own contribution to a delivered block, including alternatives considered, difficult debug and validation of the final design.

Useful experience

• Experience with inference accelerators, GPUs, TPUs or other demanding compute ASICs.
• Verilog or SystemVerilog design, with familiarity interpreting verification and implementation feedback.
• Work across design reviews, integration and block release, with clear responsibility for the logic delivered.
• Around 5–10 years of experience is a useful guide, with flexibility for engineers who demonstrate strong implementation depth.