Principal Microarchitect

Acceler8 Talent is seeking a Principal Micro-Architect to join an early stage startup backed by a Tier-1 VC that is rethinking AI infrastructure from first principles.

Founded by highly respected industry veterans, they are innovating at the chip and system level to deliver an order of magnitude better performance-per-watt for inference, which would mean a huge economic shift for anyone running large scale models, unlocking larger context windows and longer generations, making new workloads economically viable.

Responsibilities:

 ● Design data movement pipelines, together with scheduling algorithms, and control logic to integrate overall SoC architecture components

 ● Define datapaths including scratchpads memories, buffers, NoCs, and crossbars

 ● Use performance modeling and profiling to guide architecture decisions

 ● Optimize for performance, utilization, power, and area

 ● Work closely with compiler, kernel, and performance teams

 ● Evaluate ISA / programming model trade-offs

 ● Support RTL implementation, verification, and timing closure

 ● Participate in emulation, bring-up, and post-silicon performance tuning

 ● Debug real silicon issues and close performance gaps

Qualifications:

 ● Expert understanding of: NOCs, buffering, switches, memories, cross bars, and scheduling, as evidenced by leading the design & implementation of units with these structures, spanning multiple generations of process technology

 ● Direct experience in AI compute or accelerator design

 ● Performance per watt optimization

 ● Experience delivering real silicon

 ● Startup or early-stage silicon programs is a strong plus

 ● MS or PhD and 5-10 years of experience, or equivalent

If you're looking for massive ownership, huge impact, and the opportunity to build from the ground up, please apply here or reach out to me at ltomaszko@acceler8talent.com to hear more.