RTL Design Engineer

A high-growth AI hardware company is hiring RTL Design Engineers to help develop next-generation compute platforms for large-scale machine learning workloads. The team is building vertically integrated silicon and system solutions designed to power advanced AI training and inference with exceptional efficiency and performance.

This is an opportunity to work across architecture and RTL, delivering complex SoC designs that sit at the core of modern AI infrastructure.

What You’ll Do:

• Contribute to scalable architecture-to-RTL methodologies spanning block, subsystem, and full-chip design
• Own subsystem and/or chip-level deliverables from microarchitecture definition through sign-off-ready RTL
• Drive design reviews and milestone tracking, including progress toward area and timing closure, design freeze, and tapeout
• Partner closely with Verification, DFT, and Physical Design teams to achieve best-in-class Performance, Power, and Area (PPA)
• Support structured handoff and collaboration across downstream siliconization flows

What We’re Looking For:

• Proven concept-to-production experience delivering ASIC/SoC subsystems or top-level designs from architectural specification through silicon
• Strong hands-on experience with SystemVerilog, Python, C/C++, Bluespec, or similar languages used in chip development
• Demonstrated experience designing high-performance compute architectures (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related subsystems
• Experience validating your own designs and partnering with verification teams to achieve performance targets and coverage closure
• Hands-on experience with synthesis, equivalence checking, linting, clock-domain crossing analysis, and related sign-off flows
• Working knowledge of DFT and physical design methodologies to enable high test coverage and optimized timing, power, and area

Nice to Have:

• Familiarity with verification and emulation platforms and methodologies
• Experience participating in silicon bring-up and post-silicon debug
• Hands-on experience implementing silicon and firmware-based hardware security features such as Root of Trust (RoT), secure boot, lifecycle state machines, key management, TRNG interfaces, secure debug, secure firmware updates, access control, and memory protection

This role is ideal for engineers who want deep ownership of complex SoC design and to directly contribute to the silicon enabling the next wave of AI systems.