RTL Engineer
GW62
Posted: 22/09/2025
- $200,000-$300,000
- Mountain View, CA
- Permanent
About the job
Acceler8 Talent is working with a startup at the forefront of AI compute, developing advanced silicon designed to handle the largest machine learning and generative AI workloads. They are seeking a RTL engineer with a strong background in top-level integration to help deliver high-performance, functionally robust silicon across compute, memory, and high-speed interconnect technologies.
This role is ideal for engineers who thrive at the full-chip level, bringing together subsystems, resolving interface challenges, and ensuring the design is sign-off ready.
Responsibilities include:
- Driving top-level RTL integration efforts, from subsystem assembly to complete chip-level design
- Translating architecture specifications into sign-off quality RTL for large-scale ASIC/SoC programs
- Managing reviews and milestones for integration progress, ensuring timing, area, and power targets are consistently met
- Collaborating across verification, DFT, and physical design teams to ensure integrated subsystems meet quality and performance goals
- Supporting synthesis, lint, CDC, and equivalence checking activities to validate top-level correctness and readiness for tapeout
- Contributing to silicon bring-up and debug by ensuring top-level RTL integration reflects real-world system behavior
Ideal background:
- Proven concept-to-silicon experience with ASIC/SoC programs, particularly in top-level or subsystem integration
- Strong proficiency in RTL design (SystemVerilog) with working knowledge of scripting (Python, Tcl, C/C++ or similar) to support design and flow automation
- Solid track record of delivering integrated silicon in areas such as compute, interconnects, and memory subsystems
- Familiarity with synthesis and sign-off flows, including timing closure, power optimization, lint, CDC, and equivalence checking
- Experience collaborating with verification, DFT, and physical design teams to resolve integration issues at the full-chip level
- Exposure to emulation, silicon validation, and bring-up considered a plus
Mia Macdonald
Semiconductor & Chip Design Recruiter