Senior Principal design Engineer
GW70
Posted: 30/09/2025
- $240,000-$260,000
- Santa Clara, CA
- Permanent
About the job
Are you an experienced microarchitect and RTL design engineer who wants to design best-in-class NPU cores?
Acceler8 Talent is seeking a Senior Principal ASIC Design Engineer to join a unique AI hardware startup (actually generating substantial revenue) that is building the next generation of edge AI processors, capable of running generative AI models at the edge.
As a Senior Principal Design Engineer, you will be joining a talented and motivated team where you will be playing a significant role in developing the microarchitecture and implementing
in RTL for their second generation Neural Processing Unit.
Requirements
- Bachelors or Masters in Electrical or Computer Engineering
- 10+ years of industry experience working in RTL design and microarchitecture
- Deep understanding of how to optimize designs for PPA constraints.
- Strong experience working on large, complex data center/network processors
- Experience with multiple clock domains and asynchronous interfaces.
The position will be onsite from their Santa Clara office and they are looking for someone to start right away. Compensation on offer is $250k-$275k base + bonus + RSUs.
Please apply here or contact me at ltomaszko@acceler8talent.com to hear more.
Luke Tomaszko
Senior Semiconductor & Chip Design Recruiter