SoC Architect

GW61
  • $225,000-$275,000
  • United States
  • Permanent

About the job


SoC Security Architect


Acceler8 Talent is hiring an experienced SoC Architect with deep expertise in secure computing to shape the next generation of AI inference systems at a leading AI hardware startup.



This position centers on defining and implementing a secure I/O and compute subsystem, ensuring end-to-end protection from initial boot through runtime in virtualized, multi-tenant environments.



You will play a key role in embedding and integrating advanced security features including Root of Trust (RoT), secure boot, endpoint protection, encryption modules, and isolation mechanisms across firmware and hardware layers. The scope includes developing secure PCIe interfaces, memory encryption (covering technologies such as LPDDR5 and HBM), DMA protections, and trusted RISC-V cores tasked with orchestration and policy control.



Responsibilities include:

  • Creating and refining secure boot procedures, authentication systems, and RoT frameworks tailored for PCIe-based accelerator platforms
  • Designing SoC-level and IP-level safeguards such as encrypted memory, hardened debug access, and isolation between host and compute domains
  • Selecting and integrating cryptographic engines, key management modules, and monitoring infrastructure dedicated to security
  • Working closely with firmware, system software, and verification teams to deliver cohesive secure hardware/software solutions
  • Applying and adhering to recognized security standards and certification programs such as NIST, TCG, and PSA Certified
  • Supporting silicon bring-up and contributing to the validation of security features on hardware



Ideal background:

  • Advanced degree (BS/MS/PhD) in Electrical Engineering, Computer Science, or similar, with 10+ years of SoC development experience
  • Strong grounding in hardware security, trusted execution environments, and secure memory architectures
  • Hands-on experience implementing secure boot, key provisioning, and secure debug/test protocols
  • Knowledge of PCIe Gen4/5, SR-IOV, and virtualization with security in mind
  • Familiarity with RISC-V SoCs and embedding security measures into system-level designs
  • Understanding of SystemVerilog and UVM-based verification methodologies is beneficial


Mia Macdonald Semiconductor & Chip Design Recruiter

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