The 4 Silicon Photonics Roles US Fabs Cannot Fill in 2027

Silicon photonics is forecast to grow from $2.3bn in 2026 to $17.8bn by 2035, a 25.3% annual rate. US hiring is not keeping pace. Four role families carry most of what our photonics desk is briefed on, and one of them has no reliable published salary band at all.

Key takeaways

• The silicon photonics market was $1.8bn in 2025 and is forecast to reach $7bn by 2031 and $17.8bn by 2035, a 25.3% compound annual rate across 2026 to 2035 (Global Market Insights, December 2025).
• North America holds the largest regional share at 38.8%, worth $734.14m, and data centre and HPC is the largest application segment at $1.3bn.
• Co-packaged optics moved photonics inside the switch package, with NVIDIA citing 3.5 times better power efficiency and four times fewer lasers against pluggable optics.
• A US silicon photonics engineer averages $106,386 a year against a $280,000 median total compensation for a machine learning engineer, which is why the same graduates do not choose photonics.
• Silicon photonics test engineer carries only two reported salary submissions on Glassdoor, both from 2022 and 2023, so the role has no current published benchmark.

Why photonics hiring changed in 2026

Demand stopped coming from telecoms and started coming from AI compute. Data centre and HPC is now the largest application segment at $1.3bn of a $1.8bn 2025 market, and transceivers are the largest product segment at $1.3bn.

Four companies hold 58.6% of the market between them: Intel at 21.5%, Cisco at 17.6%, Broadcom at 11.5% and Lumentum at 8.0%. That concentration means a hiring brief at any one of them moves the available pool for everyone else.

What is co-packaged optics doing to the role mix?

It moves the optical engine from a pluggable module into the switch package, which turns an optics supply question into a silicon integration question. The engineer who qualified a pluggable transceiver is not the engineer who co-designs an optical engine alongside an ASIC.

NVIDIA set out the engineering case when it announced Spectrum-X Photonics and Quantum-X Photonics at GTC on 18 March 2025, citing 1.6 Tb/s per port, 3.5 times better power efficiency, four times fewer lasers, 63 times greater signal integrity and 10 times better resiliency against traditional methods. Founder and chief executive Jensen Huang framed the driver in the company’s own announcement: “AI factories are a new class of data centers with extreme scale.” The Spectrum-X Photonics switches ship from 2026, with TSMC, Coherent, Corning, Foxconn, Lumentum and SENKO named as ecosystem partners. Our earlier piece on how AI compute reshaped photonics demand traces the same shift from the demand side.

The four roles that are not filling

These are the four role families our US photonics desk is briefed on most often. They map to distinct skill sets with almost no interchangeability between them, which is why a shortlist for one does not help with another.

Design engineer and process engineer figures from ZipRecruiter, dated 11 August 2026 and 28 August 2026 respectively.

Why can’t integrated photonics design engineers be found?

Because the skill is built on a specific foundry process design kit, and there are few of them. A designer who has taped out on one platform carries knowledge of that platform’s device library, not a transferable qualification, so the pool for any given programme is a fraction of the pool for photonics overall.

Pay compounds it. The ZipRecruiter average of $106,386 sits at the 25th percentile of general US machine learning engineering compensation, so a physics or electrical engineering graduate choosing between the two is choosing between $106,386 and a $280,000 median. Reskilling adjacent engineers is the realistic route, and our note on moving existing semiconductor staff into new specialisms covers how that works in practice.

What makes photonic layout design so specialised?

Waveguides are not wires. Bend radius, mode confinement and crosstalk constrain the routing in ways electrical layout rules do not describe, and the design rule checks come from a photonics PDK rather than a standard digital flow.

That combination produces a role where neither a conventional IC layout engineer nor an optical designer is a direct fit. The absence of a published salary band is a symptom rather than an oddity: a role with no benchmark is a role too thinly populated for the aggregators to measure, and employers end up setting a number from one prior hire.

Why are fabrication and process engineers scarce?

Because the process runs on a CMOS line while the device physics is optical, so the engineer has to hold both. Yield excursions in a photonic process show up as optical loss or wavelength shift rather than as electrical failure, and diagnosing that needs process control experience plus photonic device understanding.

This is the lowest-paid of the four families at a $92,018 average and a $74,100 to $100,400 typical range, which is the weakest competitive position of any role on this list against adjacent semiconductor process work. The wider pattern sits in the talent gaps running through semiconductor engineering.

What is holding back test development hiring?

The role did not exist at volume until recently, so there is no established career path feeding it. Optical test development needs fibre alignment, wavelength-swept measurement and automation scripting together, and that combination is usually assembled on the job rather than hired in.

The data gap proves the point. Glassdoor holds two reported submissions for silicon photonics test engineer in the United States, dated 1 June 2022 and 30 August 2023, with a stated total pay range of $80,000 to $142,000 and a $106,000 median. Two submissions three and four years old is not a 2027 benchmark, and we are not treating it as one.

Why the pay band is part of the problem

Photonics competes for the same graduates as AI software and loses on headline numbers. A $106,386 average against a $280,000 median total compensation is a 2.63 times gap, calculated as $280,000 divided by $106,386.

That gap is not closable by one employer acting alone, which leaves three levers: reskill from adjacent disciplines, widen the geography, or restructure the role so the scarce skill is one component rather than the whole specification. Adaptability is the trait that makes the first of those work, and why adaptable skills decide semiconductor careers sets out what to screen for.

How to fill a silicon photonics role

Step 1. Name the foundry platform in the brief. PDK experience is platform-specific, so “silicon photonics designer” returns a pool that mostly cannot tape out on your process. State the platform and the pool shrinks honestly rather than wasting a shortlist.

Step 2. Split layout from device design. These are separate role families with separate skill sets. A combined specification will either fill slowly or fill with someone strong at one half.

Step 3. Benchmark against AI software, not against photonics. Candidates are choosing between a $106,386 average and a $280,000 median elsewhere. Price against the alternative they are weighing, not against the role’s own historic band.

Step 4. Build a reskilling route for process and test. Fabrication and test development have the thinnest direct pools, and both are learnable by adjacent semiconductor engineers inside a structured programme.

Step 5. Set the test development number from your own data. With two public submissions dated 2022 and 2023, there is no usable external benchmark, so anchor on your internal equivalents rather than a published figure.

Step 6. Move inside two weeks on design candidates. Four companies hold 58.6% of the market and all of them are hiring, so a designer who has taped out on your platform is in more than one process.

Silicon photonics hiring questions

Which silicon photonics roles are hardest to fill in the US?

Photonic layout design and photonics test development, both of which lack a reliable published salary band. Integrated photonics design and fabrication process engineering follow, with averages of $106,386 and $92,018 respectively, according to ZipRecruiter data from August 2026.

What does a silicon photonics engineer earn in the US?

An average of $106,386 a year, with a $93,600 median, a 25th percentile of $75,500 and a 75th of $132,800, as at 11 August 2026. Silicon photonics process engineers average $92,018 with a $74,100 to $100,400 typical range.

Why is silicon photonics hiring growing so fast?

Because AI compute replaced telecoms as the main driver. Data centre and HPC is the largest application segment at $1.3bn of a $1.8bn 2025 market, and the sector is forecast to reach $17.8bn by 2035 at a 25.3% compound annual rate.

What is co-packaged optics and why does it change hiring?

It integrates the optical engine into the switch package rather than a pluggable module. NVIDIA cites 3.5 times better power efficiency and four times fewer lasers against traditional methods. The integration work needs silicon and photonic design together, which is a different brief from qualifying transceivers.

Can semiconductor engineers move into photonics?

Yes, and for fabrication and test development it is the realistic route. Process integration and test engineers carry transferable process control and automation skills, with the photonic device physics learned on the job inside a structured programme rather than hired in.

Acceler8 Talent recruits across device design, layout, process and test for US photonics programmes. Our silicon photonics recruitment desk works to the foundry platform rather than the job title, because that is what decides whether a candidate can actually tape out on your process. Tell us the platform, the role family and the deadline.

About the Author

Matthew Ferdenzi is Co-Founder of Acceler8 Talent, a US-focused recruitment firm specialising in AI, machine learning, semiconductor and high-performance computing hiring. He leads the firm’s semiconductor and chip design practice, which covers silicon photonics device design, layout, process and test hiring for US fabs and fabless teams. His profile is at acceler8talent.com/about-us/meet-the-team/profile/matthew-ferdenzi.