ASIC Design Verification Engineer
BBBH10335_1712846726
Posted: 11/04/2024
- US$200000 - US$230000 per annum + Equity Package
- San Jose, California
- Permanent
Acceler8 Talent has recently partnered with a leading startup specializing in next-generation interconnect technologies designed for the future of HPC and AI applications. The company has successfully closed a large Series A funding round and secured a significant partnership with a global industry leader.
They are looking for a Senior/Principal ASIC Design Verification Engineer who is an expert with PCIe and CXL to help them accelerate AI cloud computing.
As a Design Verification Engineer with this company you will work with test bench development using System Verilog and UVM as well as develop comprehensive test plans and cases with functional coverage, assertions, and coverage properties. You will also handle regression setup and debug at both RTL and gate sim levels in collaboration with the design team.
Requirements:
- Possess a minimum of 10 years of experience in Design Verification.
- Demonstrate extensive expertise in System Verilog, UVM, and verification coverage metrics.
- Have familiarity with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP.
- Showcase robust proficiency in PCIe/CXL protocol, encompassing PHY/DLLP/TLP aspects.
- Exhibit a deep understanding of peripheral protocols like UART, I2C, and SPI Flash.
- Capable of proficiently scripting in Perl.
If you are interested in working on the forefront of interconnect technologies and AI cloud acceleration, please feel free to apply here or reach out directly at Jwhitcomb@acceler8talent.com
Jake Whitcomb
Recruitment Executive