Design Verification Engineer

Design Verification Engineer

Location: Mountain View, CA

Industry: AI Hardware / Accelerators

About the Role

A fast-growing AI hardware company is looking for an experienced Design Verification Engineer with 5+ years of pre-silicon verification experience across complex IP, subsystems, and/or SoC-level environments.

This is a senior individual-contributor role with end-to-end ownership of verification from planning through functional closure. You’ll work closely with hardware-design and software teams to help drive a next-generation AI accelerator program from pre-silicon development through first silicon and scale-out.

What You’ll Do

• Own an entire verification and testing domain based on your technical expertise.
• Develop end-to-end verification strategies spanning IP, subsystem, SoC, and emulation environments.
• Drive verification planning, implementation, debug, and functional closure for complex accelerator silicon.
• Build and improve verification infrastructure, testbenches, and methodologies.
• Debug complex functional issues across IP, subsystem, and full-chip environments.
• Partner closely with RTL design, architecture, software, and other engineering teams.
• Use and develop AI-assisted and agentic tool flows to accelerate verification and emulation timelines.
• Adapt quickly across verification domains as designs and project requirements evolve.

What We’re Looking For

• 5+ years of pre-silicon design verification experience.
• Strong end-to-end verification ownership, from verification planning through functional closure.
• Experience in one or more of the following:
• Block-level or subsystem verification
• CPU subsystem or IP integration
• SoC or full-chip verification
• Emulation testing
• DMA or NoC verification
• Multi-SoC or die-to-die protocol verification
• Strong debugging skills for complex IP, subsystem, or SoC designs.
• Deep experience with UVM methodology and testbench architecture.
• Ability to analyze and interpret specifications from both hardware and software perspectives.
• Proven experience delivering verification milestones against aggressive schedules.
• Strong collaboration skills and the ability to work across hardware, software, architecture, and verification teams.
• Interest in improving verification methodologies using modern automation and AI-assisted tooling.
• Ability to contribute across multiple verification domains as needed.

Nice to Have

• RISC-V verification experience.
• Formal verification.
• Emulation platforms such as Palladium, Veloce, or equivalent.
• Post-silicon bring-up experience.
• AI accelerator, GPU, or advanced SoC verification experience.
• Experience with NoC, DMA, chiplet, or die-to-die architectures.

Keywords:

Design Verification, DV, Pre-Silicon Verification, UVM, SystemVerilog, Testbench Architecture, Functional Verification, Functional Closure, SoC Verification, Full-Chip Verification, Subsystem Verification, Block-Level Verification, CPU Verification, CPU Subsystem, IP Integration, DMA Verification, NoC Verification, Network-on-Chip, Die-to-Die, Chiplet, Multi-SoC, Emulation, Palladium, Veloce, Formal Verification, RISC-V, Post-Silicon, Hardware Debug, AI Accelerator, ASIC Verification.