Microarchitect - Dataflows

Acceler8 Talent is working with a venture-backed startup operating in stealth mode to hire a Microarchitect to design their data movement flows.

The company is focused on developing advanced AI inference systems at the rack level. Their approach centers on a differentiated system-on-chip architecture that enables innovations across the full system stack, targeting highly efficient inference at data center scale, to build both custom hardware and extending open-source software to support next-generation AI models with strong performance and efficiency gains.

This position is focused on defining and implementing data movement strategies within a cutting-edge SoC built on an advanced process node. The role spans architecture, microarchitecture, and hardware–software co-design, with ownership from early-stage design through silicon bring-up.

Key Responsibilities

• Architect and implement data movement flows, including scheduling strategies and control mechanisms, to support integration across SoC components
• Define and optimize datapath elements such as on-chip memories, buffering structures, interconnects, and switching fabrics
• Apply performance modeling and analysis to inform architectural trade-offs and decisions
• Drive optimizations across key metrics including throughput, efficiency, power consumption, and silicon area
• Collaborate cross-functionally with compiler, kernel, and performance engineering teams
• Assess trade-offs related to instruction set design and programming models
• Contribute to RTL development, verification efforts, and timing closure activities
• Support emulation, system bring-up, and post-silicon tuning efforts
• Diagnose and resolve issues observed in silicon, working to close performance gaps

Qualifications

• Deep expertise in interconnects, memory hierarchies, buffering strategies, switching fabrics, and scheduling mechanisms, demonstrated through ownership of relevant hardware designs across multiple process generations
• Experience working on AI accelerators or similar high-performance compute architectures
• Strong focus on performance-per-watt optimization
• Proven track record of contributing to successful silicon bring-up
• Background in early-stage or startup hardware programs is advantageous
• Advanced degree (MS or PhD) with approximately 5–10 years of relevant experience, or equivalent practical experience