Design Verification Engineer

Design Verification (DV) Engineer

Mountain View, CA

About the Role

A venture-backed semiconductor company is seeking an experienced Design Verification Engineer to help verify a new generation of advanced compute silicon.

This is a senior individual-contributor role focused on end-to-end pre-silicon verification across complex IP, subsystems, and full-chip designs. You will work closely with hardware design, architecture, emulation, and software teams to drive verification from planning through functional closure and support the transition toward silicon bring-up.

What You’ll Do

• Own a complete verification domain based on your technical expertise.
• Develop end-to-end verification strategies spanning block, subsystem, SoC, and emulation environments.
• Build verification plans, testbenches, stimulus, checkers, assertions, coverage models, and regression infrastructure.
• Drive functional coverage and bug closure for complex silicon designs.
• Verify key areas such as CPU subsystems, DMA, on-chip interconnects, multi-die interfaces, or system-level integration.
• Partner with design and software teams to understand specifications and validate behavior across the hardware-software boundary.
• Improve verification efficiency through automation and modern assisted-development tools.
• Define clear milestones and deliverables while adapting to a fast-moving design cycle.
• Contribute across additional verification domains when needed.

What We’re Looking For

• 5+ years of pre-silicon design verification experience.
• Proven ownership of verification from planning through functional closure.
• Experience in one or more of the following:
• Block-level or subsystem verification
• CPU subsystem or IP integration
• SoC or full-chip verification
• Hardware emulation
• DMA or network-on-chip verification
• Multi-chip, multi-die, or die-to-die protocol verification
• Strong experience with SystemVerilog, UVM, testbench architecture, constrained-random verification, assertions, and coverage-driven verification.
• Ability to debug complex functional failures across IP, subsystem, and SoC environments.
• Strong understanding of hardware specifications and software-visible behavior.
• Experience defining verification goals, schedules, milestones, and closure criteria.
• Ability to work independently while collaborating closely with cross-functional engineering teams.
• Flexibility to contribute across multiple verification areas in a dynamic development environment.

Preferred Experience

• RISC-V or other modern processor architectures.
• Formal verification.
• Hardware acceleration or emulation platforms.
• Post-silicon validation and bring-up.
• Verification of AI accelerators, GPUs, CPUs, or other high-performance compute silicon.
• Verification automation using Python, scripting, or assisted engineering tools.

Relevant Keywords

Design Verification, ASIC Verification, SoC Verification, IP Verification, Subsystem Verification, Full-Chip Verification, Block-Level Verification, SystemVerilog, UVM, SVA, Constrained-Random Verification, Coverage-Driven Verification, Functional Coverage, Code Coverage, Assertion-Based Verification, Testbench Architecture, Verification Planning, Regression Testing, Debug, Functional Closure, CPU Verification, CPU Subsystem Verification, IP Integration, DMA Verification, NoC Verification, Interconnect Verification, Multi-Die Verification, Chiplet Verification, Die-to-Die Protocols, Emulation, Hardware Acceleration, Palladium, Veloce, Formal Verification, RISC-V, Post-Silicon Bring-Up, AI Accelerator Verification, GPU Verification, CPU Verification, Python, C++, Verdi, VCS, Xcelium