RTL Design Engineer

🚨 Founding RTL Design Engineer – AI Inference ASIC

📍 Full-time onsite, South Bay

I’m working with a seed-funded stealth company building a dedicated LLM inference chip and the software stack around it.

They’re designing hardware and software together to tackle one of AI’s biggest challenges: delivering more inference throughput and faster responses while reducing power consumption and cost.

The company has raised tens of millions in seed funding and brings together Stanford AI researchers with experienced silicon engineers from NVIDIA, Groq and Google, including extensive TPU tapeout experience. With hardware leadership in place, they’re now building the early senior engineering team.

This is a high-ownership role for someone who wants to personally build a meaningful part of the first chip, work directly with the founders and help shape a new inference platform.

You’ll work on:

• Implementing and debugging RTL for a purpose-built inference ASIC
• Translating microarchitecture into digital logic
• Owning a defined part of the chip from design through implementation and debugging
• Solving difficult logic and microarchitecture problems
• Working closely with verification engineers to establish correctness and resolve design issues
• Collaborating with physical implementation teams to address design constraints
• Working directly with founders and experienced silicon engineers to iterate and deliver

Requirements:

✅ Strong personal ownership of RTL implementation for a digital ASIC or SoC

✅ Evidence of solving difficult logic or microarchitecture problems through your own implementation

✅ Experience working with verification and implementation teams to resolve design issues

✅ Ability to explain your technical decisions, tradeoffs and individual contributions in depth

✅ Staff, Senior Staff or Principal-level technical depth; exceptional engineers earlier in their careers will also be considered

✅ Enthusiasm for detailed, hands-on engineering in a small founding team

✅ Comfort taking ownership and delivering independently in an early-stage environment

✅ Willingness to work full-time onsite in the South Bay

⭐ Inference ASIC or AI accelerator experience is especially valuable, with strong adjacent digital ASIC, SoC or compute-silicon experience also considered

💰 Package: $250K–$400K cash compensation + meaningful early-stage equity.