Senior Physical Design Engineer

A well-funded, early-stage AI hardware company is developing next-generation silicon to power high-performance and efficient generative AI systems. The team is focused on pushing the limits of performance and energy efficiency across advanced compute architectures at leading-edge process nodes.

The founding team includes experienced engineers from top semiconductor and technology companies, and the company has recently secured record-breaking funding with multi-year runway.

Role Overview

The team is seeking an experienced Silicon Physical Design Engineer to contribute to the development of high-performance ASICs across compute, memory, and high-speed interconnect domains. This role involves ownership across the full physical design flow, from RTL through tapeout.

Key Responsibilities

• Contribute to and evolve Physical Design methodologies across block, subsystem, and full-chip levels (RTL to GDSII)
• Own physical design execution for subsystems or full-chip deliverables, including:
• Partitioning and floorplanning
• Synthesis, place & route, and clocking
• Timing, power, EMIR, and physical verification sign-off
• Plan and drive design reviews, tracking progress toward key milestones (e.g., design freeze, tapeout)
• Collaborate closely with Design, Verification, and DFT teams to optimize performance, power, and area (PPA)
• Support scalable and repeatable implementation strategies across complex silicon programs

Required Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent
• 8+ years of experience in ASIC Physical Design
• Proven experience owning physical design from early RTL through production silicon
• Strong understanding of full physical design flow and sign-off methodologies
• Proficiency in scripting and automation (e.g., Python, TCL, Perl)
• Experience working cross-functionally with Design, Verification, and DFT teams
• Strong communication and collaboration skills

Preferred Qualifications

• Experience with advanced process nodes and high-performance designs
• Background working with or managing third-party design services partners
• Experience in AI, HPC, or other compute-intensive silicon domains